github/AROS-v0
1
0
Fork 0
mirror of https://github.com/deadw00d/AROS.git synced 2025-10-26 21:18:42 +00:00
Code Issues Releases Wiki Activity

adjust riscv case, so the definitions are provided for other flavours.

Browse Source
This commit is contained in:
Kalamatee
2025-09-15 00:27:45 +01:00
committed by deadwood
parent 709ffb52d3
commit afd9ecd056
2 changed files with 54 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
configure vendored
View File

@ -10922,31 +10922,32 @@ printf "%s\n" "$darwin_sdk_path" >&6; }
esac
;;
native)
native*)
aros_flavour="standalone"
aros_target_arch="native"
aros_object_format="riscvelf_aros"
aros_isa_flags="$""(ISA_RISCV_FLAGS)"
aros_shared_default="no"
llvm_target_cpu="RISCV"
case "$target_cpu" in
*riscv64*)
PLATFORM_EXECSMP="#define __AROSPLATFORM_SMP__"
aros_target_cpu="riscv64"
gcc_default_cpu="rv64imafdc"
gcc_default_mode="lp64d"
;;
*riscv*)
aros_target_cpu="riscv"
gcc_default_cpu="rv32imafdc"
gcc_default_mode="ilp32d"
;;
*)
as_fn_error $? "\"Unsupported CPU '$target_cpu' for RISCV\"" "$LINENO" 5
;;
esac
case "$aros_target_variant" in
*sifive_u*)
aros_flavour="standalone"
aros_target_arch="native"
aros_object_format="riscvelf_aros"
aros_isa_flags="$""(ISA_RISCV_FLAGS)"
aros_shared_default="no"
llvm_target_cpu="RISCV"
case "$target_cpu" in
*riscv64*)
PLATFORM_EXECSMP="#define __AROSPLATFORM_SMP__"
aros_target_cpu="riscv64"
gcc_default_cpu="rv64imafdc"
gcc_default_mode="lp64"
;;
*riscv*)
aros_target_cpu="riscv"
gcc_default_cpu="rv32imafdc"
gcc_default_mode="ilp32"
;;
*)
as_fn_error $? "\"Unsupported CPU '$target_cpu' for SiFive Unleashed\"" "$LINENO" 5
;;
esac
;;
esac
;;
@ -18986,6 +18987,9 @@ printf "%s\n" "$kernel_optimization_level" >&6; }
case "$aros_target_cpu" in
riscv)
export_target_gcccpu="yes"
;;
arm)
export_target_gcccpu="yes"
;;

50
configure.in
View File

@ -2070,31 +2070,32 @@ case "$target_os" in
esac
;;
native)
native*)
aros_flavour="standalone"
aros_target_arch="native"
aros_object_format="riscvelf_aros"
aros_isa_flags="$""(ISA_RISCV_FLAGS)"
aros_shared_default="no"
llvm_target_cpu="RISCV"
case "$target_cpu" in
*riscv64*)
PLATFORM_EXECSMP="#define __AROSPLATFORM_SMP__"
aros_target_cpu="riscv64"
gcc_default_cpu="rv64imafdc"
gcc_default_mode="lp64d"
;;
*riscv*)
aros_target_cpu="riscv"
gcc_default_cpu="rv32imafdc"
gcc_default_mode="ilp32d"
;;
*)
AC_MSG_ERROR("Unsupported CPU '$target_cpu' for RISCV")
;;
esac
case "$aros_target_variant" in
*sifive_u*)
aros_flavour="standalone"
aros_target_arch="native"
aros_object_format="riscvelf_aros"
aros_isa_flags="$""(ISA_RISCV_FLAGS)"
aros_shared_default="no"
llvm_target_cpu="RISCV"
case "$target_cpu" in
*riscv64*)
PLATFORM_EXECSMP="#define __AROSPLATFORM_SMP__"
aros_target_cpu="riscv64"
gcc_default_cpu="rv64imafdc"
gcc_default_mode="lp64"
;;
*riscv*)
aros_target_cpu="riscv"
gcc_default_cpu="rv32imafdc"
gcc_default_mode="ilp32"
;;
*)
AC_MSG_ERROR("Unsupported CPU '$target_cpu' for SiFive Unleashed")
;;
esac
;;
esac
;;
@ -3817,6 +3818,9 @@ dnl if needed.
dnl
case "$aros_target_cpu" in
riscv)
export_target_gcccpu="yes"
;;
arm)
export_target_gcccpu="yes"
;;