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@R added different macros.h

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This commit is contained in:
bebbo
2017-01-10 00:29:48 +01:00
parent a82fbf676a
commit d2465b6b40
1 changed files with 290 additions and 144 deletions
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patches/NDK_3.9/Include/include_h/inline/macros.h
+290 -144
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@@ -24,53 +24,67 @@
#define LP0(offs, rt, name, bt, bn) \
({ \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP0NR(offs, name, bt, bn) \
({ \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
#define LP1(offs, rt, name, t1, v1, r1, bt, bn) \
({ \
t1 _##name##_v1 = (v1); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP1NR(offs, name, t1, v1, r1, bt, bn) \
({ \
t1 _##name##_v1 = (v1); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -78,16 +92,19 @@
#define LP1A5(offs, rt, name, t1, v1, r1, bt, bn) \
({ \
t1 _##name##_v1 = (v1); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
__asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
/* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom() */
@@ -95,12 +112,16 @@
({ \
t1 _##name##_v1 = (v1); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
__asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -109,33 +130,39 @@
({ \
typedef fpt; \
t1 _##name##_v1 = (v1); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
__asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn) \
({ \
t1 _##name##_v1 = (v1); \
t2 _##name##_v2 = (v2); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn) \
@@ -143,13 +170,17 @@
t1 _##name##_v1 = (v1); \
t2 _##name##_v2 = (v2); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -158,16 +189,19 @@
({ \
t1 _##name##_v1 = (v1); \
t2 _##name##_v2 = (v2); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r"(_n1), "rf"(_n2) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
/* Only dos.library/InternalUnLoadSeg() */
@@ -176,17 +210,20 @@
typedef fpt; \
t1 _##name##_v1 = (v1); \
t2 _##name##_v2 = (v2); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
@@ -194,18 +231,21 @@
t1 _##name##_v1 = (v1); \
t2 _##name##_v2 = (v2); \
t3 _##name##_v3 = (v3); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
@@ -214,14 +254,18 @@
t2 _##name##_v2 = (v2); \
t3 _##name##_v3 = (v3); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -231,17 +275,20 @@
t1 _##name##_v1 = (v1); \
t2 _##name##_v2 = (v2); \
t3 _##name##_v3 = (v3); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r"(_n1), "rf"(_n2), "rf"(_n3) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
/* Only cia.resource/RemICRVector() */
@@ -251,13 +298,17 @@
t2 _##name##_v2 = (v2); \
t3 _##name##_v3 = (v3); \
{ \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r"(_n1), "rf"(_n2), "rf"(_n3) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -268,18 +319,21 @@
t1 _##name##_v1 = (v1); \
t2 _##name##_v2 = (v2); \
t3 _##name##_v3 = (v3); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
/* Only graphics.library/SetCollision() */
@@ -290,14 +344,18 @@
t2 _##name##_v2 = (v2); \
t3 _##name##_v3 = (v3); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -307,19 +365,22 @@
t2 _##name##_v2 = (v2); \
t3 _##name##_v3 = (v3); \
t4 _##name##_v4 = (v4); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
register t4 _n4 __asm(#r4) = _##name##_v4; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
@@ -329,15 +390,19 @@
t3 _##name##_v3 = (v3); \
t4 _##name##_v4 = (v4); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
register t4 _n4 __asm(#r4) = _##name##_v4; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -349,19 +414,22 @@
t2 _##name##_v2 = (v2); \
t3 _##name##_v3 = (v3); \
t4 _##name##_v4 = (v4); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
register t4 _n4 __asm(#r4) = _##name##_v4; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
@@ -371,20 +439,23 @@
t3 _##name##_v3 = (v3); \
t4 _##name##_v4 = (v4); \
t5 _##name##_v5 = (v5); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
register t4 _n4 __asm(#r4) = _##name##_v4; \
register t5 _n5 __asm(#r5) = _##name##_v5; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
@@ -395,16 +466,20 @@
t4 _##name##_v4 = (v4); \
t5 _##name##_v5 = (v5); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
register t4 _n4 __asm(#r4) = _##name##_v4; \
register t5 _n5 __asm(#r5) = _##name##_v5; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -417,20 +492,50 @@
t3 _##name##_v3 = (v3); \
t4 _##name##_v4 = (v4); \
t5 _##name##_v5 = (v5); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
register t4 _n4 __asm(#r4) = _##name##_v4; \
register t5 _n5 __asm(#r5) = _##name##_v5; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
/* Only reqtools.library/XXX() */
#define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
({ \
t1 _##name##_v1 = (v1); \
t2 _##name##_v2 = (v2); \
t3 _##name##_v3 = (v3); \
t4 _##name##_v4 = (v4); \
t5 _##name##_v5 = (v5); \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
register t4 _n4 __asm(#r4) = _##name##_v4; \
register t5 _n5 __asm(#r5) = _##name##_v5; \
__asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
}); \
})
#define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
@@ -441,9 +546,12 @@
t4 _##name##_v4 = (v4); \
t5 _##name##_v5 = (v5); \
t6 _##name##_v6 = (v6); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -451,11 +559,11 @@
register t5 _n5 __asm(#r5) = _##name##_v5; \
register t6 _n6 __asm(#r6) = _##name##_v6; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
@@ -467,7 +575,11 @@
t5 _##name##_v5 = (v5); \
t6 _##name##_v6 = (v6); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -475,9 +587,9 @@
register t5 _n5 __asm(#r5) = _##name##_v5; \
register t6 _n6 __asm(#r6) = _##name##_v6; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -490,9 +602,12 @@
t5 _##name##_v5 = (v5); \
t6 _##name##_v6 = (v6); \
t7 _##name##_v7 = (v7); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -501,11 +616,11 @@
register t6 _n6 __asm(#r6) = _##name##_v6; \
register t7 _n7 __asm(#r7) = _##name##_v7; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
@@ -518,7 +633,11 @@
t6 _##name##_v6 = (v6); \
t7 _##name##_v7 = (v7); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -527,9 +646,9 @@
register t6 _n6 __asm(#r6) = _##name##_v6; \
register t7 _n7 __asm(#r7) = _##name##_v7; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -543,9 +662,12 @@
t5 _##name##_v5 = (v5); \
t6 _##name##_v6 = (v6); \
t7 _##name##_v7 = (v7); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -554,11 +676,11 @@
register t6 _n6 __asm(#r6) = _##name##_v6; \
register t7 _n7 __asm(#r7) = _##name##_v7; \
__asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
/* Would you believe that there really are beasts that need more than 7
@@ -575,9 +697,12 @@
t6 _##name##_v6 = (v6); \
t7 _##name##_v7 = (v7); \
t8 _##name##_v8 = (v8); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -587,11 +712,11 @@
register t7 _n7 __asm(#r7) = _##name##_v7; \
register t8 _n8 __asm(#r8) = _##name##_v8; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
/* For example intuition.library/ModifyProp() */
@@ -606,7 +731,11 @@
t7 _##name##_v7 = (v7); \
t8 _##name##_v8 = (v8); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -616,9 +745,9 @@
register t7 _n7 __asm(#r7) = _##name##_v7; \
register t8 _n8 __asm(#r8) = _##name##_v8; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -634,9 +763,12 @@
t7 _##name##_v7 = (v7); \
t8 _##name##_v8 = (v8); \
t9 _##name##_v9 = (v9); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -647,11 +779,11 @@
register t8 _n8 __asm(#r8) = _##name##_v8; \
register t9 _n9 __asm(#r9) = _##name##_v9; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
/* For example intuition.library/NewModifyProp() */
@@ -667,7 +799,11 @@
t8 _##name##_v8 = (v8); \
t9 _##name##_v9 = (v9); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -678,9 +814,9 @@
register t8 _n8 __asm(#r8) = _##name##_v8; \
register t9 _n9 __asm(#r9) = _##name##_v9; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -697,9 +833,12 @@
t8 _##name##_v8 = (v8); \
t9 _##name##_v9 = (v9); \
t10 _##name##_v10 = (v10); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -711,11 +850,11 @@
register t9 _n9 __asm(#r9) = _##name##_v9; \
register t10 _n10 __asm(#r10) = _##name##_v10; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
/* Only graphics.library/BltMaskBitMapRastPort() */
@@ -732,7 +871,11 @@
t9 _##name##_v9 = (v9); \
t10 _##name##_v10 = (v10); \
{ \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register int _d0 __asm("d0"); \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -744,9 +887,9 @@
register t9 _n9 __asm(#r9) = _##name##_v9; \
register t10 _n10 __asm(#r10) = _##name##_v10; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: /* no output */ \
: "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
} \
})
@@ -764,9 +907,12 @@
t9 _##name##_v9 = (v9); \
t10 _##name##_v10 = (v10); \
t11 _##name##_v11 = (v11); \
{ \
({ \
register int _d1 __asm("d1"); \
register int _a0 __asm("a0"); \
register int _a1 __asm("a1"); \
register rt _##name##_re __asm("d0"); \
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
register void *const _##name##_bn __asm("a6") = (bn); \
register t1 _n1 __asm(#r1) = _##name##_v1; \
register t2 _n2 __asm(#r2) = _##name##_v2; \
register t3 _n3 __asm(#r3) = _##name##_v3; \
@@ -779,11 +925,11 @@
register t10 _n10 __asm(#r10) = _##name##_v10; \
register t11 _n11 __asm(#r11) = _##name##_v11; \
__asm volatile ("jsr a6@(-"#offs":W)" \
: "=r" (_##name##_re) \
: "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10), "rf"(_n11) \
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
: "fp0", "fp1", "cc", "memory"); \
_##name##_re; \
} \
}); \
})
#endif /* __INLINE_MACROS_H */