copy inline macros from fd2sfd
This commit is contained in:
Krystian Bacławski
parent
c383c1438d
commit
5f77cdb9e4
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@ -1,23 +0,0 @@
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#ifndef _INLINE_ALIB_H
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#define _INLINE_ALIB_H
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#ifndef __INLINE_MACROS_H
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#include <inline/macros.h>
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#endif
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#define BeginIO(ioReq) \
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({ \
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struct IORequest *_BeginIO_request = (ioReq); \
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LP1NR(0x1e, BeginIO, struct IORequest *, _BeginIO_request, a1, \
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, _BeginIO_request->io_Device); \
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})
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#define NewList(list) \
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({ \
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struct List *_NewList_list = (list); \
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_NewList_list->lh_TailPred = (struct Node *)_NewList_list; \
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_NewList_list->lh_Head = (struct Node *)&_NewList_list->lh_Tail; \
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_NewList_list->lh_Tail = 0; \
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})
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#endif /* _INLINE_ALIB_H */
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@ -1,789 +0,0 @@
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#ifndef __INLINE_MACROS_H
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#define __INLINE_MACROS_H
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/*
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General macros for Amiga function calls. Not all the possibilities have
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been created - only the ones which exist in OS 3.1. Third party libraries
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and future versions of AmigaOS will maybe need some new ones...
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LPX - functions that take X arguments.
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Modifiers (variations are possible):
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NR - no return (void),
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A4, A5 - "a4" or "a5" is used as one of the arguments,
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UB - base will be given explicitly by user (see cia.resource).
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FP - one of the parameters has type "pointer to function".
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"bt" arguments are not used - they are provided for backward compatibility
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only.
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*/
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#ifndef __INLINE_STUB_H
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#include <inline/stubs.h>
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#endif
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#define LP0(offs, rt, name, bt, bn) \
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({ \
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{ \
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register rt _##name##_re __asm("d0"); \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: "=r" (_##name##_re) \
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: "r" (_##name##_bn) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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#define LP0NR(offs, name, bt, bn) \
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({ \
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{ \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: /* no output */ \
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: "r" (_##name##_bn) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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} \
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})
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#define LP1(offs, rt, name, t1, v1, r1, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: "=r" (_##name##_re) \
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: "r" (_##name##_bn), "rf"(_n1) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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#define LP1NR(offs, name, t1, v1, r1, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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{ \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: /* no output */ \
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: "r" (_##name##_bn), "rf"(_n1) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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} \
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})
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/* Only graphics.library/AttemptLockLayerRom() */
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#define LP1A5(offs, rt, name, t1, v1, r1, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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__asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \
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: "=r" (_##name##_re) \
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: "r" (_##name##_bn), "rf"(_n1) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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/* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom() */
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#define LP1NRA5(offs, name, t1, v1, r1, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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{ \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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__asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \
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: /* no output */ \
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: "r" (_##name##_bn), "rf"(_n1) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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} \
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})
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/* Only exec.library/Supervisor() */
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#define LP1A5FP(offs, rt, name, t1, v1, r1, bt, bn, fpt) \
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({ \
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typedef fpt; \
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t1 _##name##_v1 = (v1); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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__asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \
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: "=r" (_##name##_re) \
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: "r" (_##name##_bn), "rf"(_n1) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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#define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: "=r" (_##name##_re) \
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: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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#define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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{ \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: /* no output */ \
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: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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} \
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})
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/* Only cia.resource/AbleICR() and cia.resource/SetICR() */
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#define LP2UB(offs, rt, name, t1, v1, r1, t2, v2, r2) \
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({ \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: "=r" (_##name##_re) \
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: "r"(_n1), "rf"(_n2) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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/* Only dos.library/InternalUnLoadSeg() */
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#define LP2FP(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \
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({ \
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typedef fpt; \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: "=r" (_##name##_re) \
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: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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#define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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t3 _##name##_v3 = (v3); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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register t3 _n3 __asm(#r3) = _##name##_v3; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: "=r" (_##name##_re) \
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: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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#define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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t3 _##name##_v3 = (v3); \
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{ \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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register t3 _n3 __asm(#r3) = _##name##_v3; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: /* no output */ \
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: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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} \
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})
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/* Only cia.resource/AddICRVector() */
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#define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \
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({ \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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t3 _##name##_v3 = (v3); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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register t3 _n3 __asm(#r3) = _##name##_v3; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: "=r" (_##name##_re) \
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: "r"(_n1), "rf"(_n2), "rf"(_n3) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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/* Only cia.resource/RemICRVector() */
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#define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \
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({ \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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t3 _##name##_v3 = (v3); \
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{ \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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register t3 _n3 __asm(#r3) = _##name##_v3; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: /* no output */ \
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: "r"(_n1), "rf"(_n2), "rf"(_n3) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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} \
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})
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/* Only exec.library/SetFunction() */
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#define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \
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({ \
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typedef fpt; \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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t3 _##name##_v3 = (v3); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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register t3 _n3 __asm(#r3) = _##name##_v3; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: "=r" (_##name##_re) \
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: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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/* Only graphics.library/SetCollision() */
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#define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \
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({ \
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typedef fpt; \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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t3 _##name##_v3 = (v3); \
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{ \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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register t3 _n3 __asm(#r3) = _##name##_v3; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: /* no output */ \
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: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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} \
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})
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#define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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t3 _##name##_v3 = (v3); \
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t4 _##name##_v4 = (v4); \
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{ \
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register rt _##name##_re __asm("d0"); \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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register t1 _n1 __asm(#r1) = _##name##_v1; \
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register t2 _n2 __asm(#r2) = _##name##_v2; \
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register t3 _n3 __asm(#r3) = _##name##_v3; \
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register t4 _n4 __asm(#r4) = _##name##_v4; \
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__asm volatile ("jsr a6@(-"#offs":W)" \
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: "=r" (_##name##_re) \
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: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
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: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
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_##name##_re; \
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} \
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})
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#define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \
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({ \
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t1 _##name##_v1 = (v1); \
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t2 _##name##_v2 = (v2); \
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t3 _##name##_v3 = (v3); \
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t4 _##name##_v4 = (v4); \
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{ \
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register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
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||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: /* no output */ \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
} \
|
||||
})
|
||||
|
||||
/* Only exec.library/RawDoFmt() */
|
||||
#define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \
|
||||
({ \
|
||||
typedef fpt; \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
#define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
#define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
{ \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: /* no output */ \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
} \
|
||||
})
|
||||
|
||||
/* Only exec.library/MakeLibrary() */
|
||||
#define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \
|
||||
({ \
|
||||
typedef fpt; \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
#define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
#define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
{ \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: /* no output */ \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
} \
|
||||
})
|
||||
|
||||
#define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
#define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
{ \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: /* no output */ \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
} \
|
||||
})
|
||||
|
||||
/* Only workbench.library/AddAppIconA() */
|
||||
#define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
__asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
/* Would you believe that there really are beasts that need more than 7
|
||||
arguments? :-) */
|
||||
|
||||
/* For example intuition.library/AutoRequest() */
|
||||
#define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
t8 _##name##_v8 = (v8); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
register t8 _n8 __asm(#r8) = _##name##_v8; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
/* For example intuition.library/ModifyProp() */
|
||||
#define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
t8 _##name##_v8 = (v8); \
|
||||
{ \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
register t8 _n8 __asm(#r8) = _##name##_v8; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: /* no output */ \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
} \
|
||||
})
|
||||
|
||||
/* For example layers.library/CreateUpfrontHookLayer() */
|
||||
#define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
t8 _##name##_v8 = (v8); \
|
||||
t9 _##name##_v9 = (v9); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
register t8 _n8 __asm(#r8) = _##name##_v8; \
|
||||
register t9 _n9 __asm(#r9) = _##name##_v9; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
/* For example intuition.library/NewModifyProp() */
|
||||
#define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
t8 _##name##_v8 = (v8); \
|
||||
t9 _##name##_v9 = (v9); \
|
||||
{ \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
register t8 _n8 __asm(#r8) = _##name##_v8; \
|
||||
register t9 _n9 __asm(#r9) = _##name##_v9; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: /* no output */ \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
} \
|
||||
})
|
||||
|
||||
/* Kriton Kyrimis <kyrimis@cti.gr> says CyberGraphics needs the following */
|
||||
#define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
t8 _##name##_v8 = (v8); \
|
||||
t9 _##name##_v9 = (v9); \
|
||||
t10 _##name##_v10 = (v10); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
register t8 _n8 __asm(#r8) = _##name##_v8; \
|
||||
register t9 _n9 __asm(#r9) = _##name##_v9; \
|
||||
register t10 _n10 __asm(#r10) = _##name##_v10; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
/* Only graphics.library/BltMaskBitMapRastPort() */
|
||||
#define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
t8 _##name##_v8 = (v8); \
|
||||
t9 _##name##_v9 = (v9); \
|
||||
t10 _##name##_v10 = (v10); \
|
||||
{ \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
register t8 _n8 __asm(#r8) = _##name##_v8; \
|
||||
register t9 _n9 __asm(#r9) = _##name##_v9; \
|
||||
register t10 _n10 __asm(#r10) = _##name##_v10; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: /* no output */ \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
} \
|
||||
})
|
||||
|
||||
/* Only graphics.library/BltBitMap() */
|
||||
#define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \
|
||||
({ \
|
||||
t1 _##name##_v1 = (v1); \
|
||||
t2 _##name##_v2 = (v2); \
|
||||
t3 _##name##_v3 = (v3); \
|
||||
t4 _##name##_v4 = (v4); \
|
||||
t5 _##name##_v5 = (v5); \
|
||||
t6 _##name##_v6 = (v6); \
|
||||
t7 _##name##_v7 = (v7); \
|
||||
t8 _##name##_v8 = (v8); \
|
||||
t9 _##name##_v9 = (v9); \
|
||||
t10 _##name##_v10 = (v10); \
|
||||
t11 _##name##_v11 = (v11); \
|
||||
{ \
|
||||
register rt _##name##_re __asm("d0"); \
|
||||
register struct Library *const _##name##_bn __asm("a6") = (struct Library*)(bn); \
|
||||
register t1 _n1 __asm(#r1) = _##name##_v1; \
|
||||
register t2 _n2 __asm(#r2) = _##name##_v2; \
|
||||
register t3 _n3 __asm(#r3) = _##name##_v3; \
|
||||
register t4 _n4 __asm(#r4) = _##name##_v4; \
|
||||
register t5 _n5 __asm(#r5) = _##name##_v5; \
|
||||
register t6 _n6 __asm(#r6) = _##name##_v6; \
|
||||
register t7 _n7 __asm(#r7) = _##name##_v7; \
|
||||
register t8 _n8 __asm(#r8) = _##name##_v8; \
|
||||
register t9 _n9 __asm(#r9) = _##name##_v9; \
|
||||
register t10 _n10 __asm(#r10) = _##name##_v10; \
|
||||
register t11 _n11 __asm(#r11) = _##name##_v11; \
|
||||
__asm volatile ("jsr a6@(-"#offs":W)" \
|
||||
: "=r" (_##name##_re) \
|
||||
: "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10), "rf"(_n11) \
|
||||
: "d0", "d1", "a0", "a1", "fp0", "fp1", "cc", "memory"); \
|
||||
_##name##_re; \
|
||||
} \
|
||||
})
|
||||
|
||||
#endif /* __INLINE_MACROS_H */
|
||||
|
|
@ -1,141 +0,0 @@
|
|||
#ifndef __INLINE_STUB_H
|
||||
#define __INLINE_STUB_H
|
||||
|
||||
#ifndef EXEC_TYPES_H
|
||||
#include <exec/types.h>
|
||||
#endif
|
||||
#ifndef EXEC_NODES_H
|
||||
#include <exec/lists.h>
|
||||
#endif
|
||||
#ifndef DOS_DOS_H
|
||||
#include <dos/dos.h>
|
||||
#endif
|
||||
#ifndef INTUITION_CLASSES_H
|
||||
#include <intuition/classes.h>
|
||||
#endif
|
||||
#ifndef GRAPHICS_DISPLAYINFO_H
|
||||
#include <graphics/displayinfo.h>
|
||||
#endif
|
||||
#ifndef LIBRARIES_COMMODITIES_H
|
||||
#include <libraries/commodities.h>
|
||||
#endif
|
||||
|
||||
struct AnchorPath;
|
||||
struct AnimOb;
|
||||
struct AreaInfo;
|
||||
struct BitMap;
|
||||
struct BitScaleArgs;
|
||||
struct Bob;
|
||||
struct Border;
|
||||
struct Catalog;
|
||||
struct CardHandle;
|
||||
struct ClipboardHandle;
|
||||
struct ClipRect;
|
||||
struct ClockData;
|
||||
struct ColorMap;
|
||||
struct ColorWheelRGB;
|
||||
struct ColorWheelHSB;
|
||||
struct ConfigDev;
|
||||
struct CSource;
|
||||
struct CopList;
|
||||
struct CurrentBinding;
|
||||
struct DataBase;
|
||||
struct DateStamp;
|
||||
struct DateTime;
|
||||
struct Device;
|
||||
struct DeviceNode;
|
||||
struct DeviceTData;
|
||||
struct DiskObject;
|
||||
struct DosLibrary;
|
||||
struct DosList;
|
||||
struct DevProc;
|
||||
struct DosPacket;
|
||||
struct DrawInfo;
|
||||
struct EasyStruct;
|
||||
struct EClockVal;
|
||||
struct ExAllControl;
|
||||
struct ExAllData;
|
||||
struct ExecBase;
|
||||
struct ExpansionBase;
|
||||
struct FileInfoBlock;
|
||||
struct FileLock;
|
||||
struct FileRequester;
|
||||
struct FontContentsHeader;
|
||||
struct FreeList;
|
||||
struct Gadget;
|
||||
struct GadgetInfo;
|
||||
struct GelsInfo;
|
||||
struct GlyphEngine;
|
||||
struct GlyphMap;
|
||||
struct GfxBase;
|
||||
struct HelpNode;
|
||||
struct Hook;
|
||||
struct IClass;
|
||||
struct Image;
|
||||
struct InfoData;
|
||||
struct InputEvent;
|
||||
struct Interrupt;
|
||||
struct IntuiText;
|
||||
struct IntuitionBase;
|
||||
struct IORequest;
|
||||
struct KeyMap;
|
||||
struct KeyQuery;
|
||||
struct Layer;
|
||||
struct Layer_Info;
|
||||
struct Library;
|
||||
struct List;
|
||||
struct Locale;
|
||||
struct LocaleBase;
|
||||
struct MathIEEEBase;
|
||||
struct MemHeader;
|
||||
struct MemList;
|
||||
struct Menu;
|
||||
struct MenuItem;
|
||||
struct Message;
|
||||
struct MiscResource;
|
||||
struct MsgPort;
|
||||
struct NamedObject;
|
||||
struct Node;
|
||||
struct NewAmigaGuide;
|
||||
struct NewGadget;
|
||||
struct NewMenu;
|
||||
struct NewScreen;
|
||||
struct NewWindow;
|
||||
struct NotifyRequest;
|
||||
struct Preferences;
|
||||
struct RDArgs;
|
||||
struct RastPort;
|
||||
struct RealTimeBase;
|
||||
struct RecordLock;
|
||||
struct Rectangle;
|
||||
struct Region;
|
||||
struct Remember;
|
||||
struct Requester;
|
||||
struct ReqToolsBase;
|
||||
struct Resident;
|
||||
struct RexxMsg;
|
||||
struct RomBootBase;
|
||||
struct RxsLib;
|
||||
struct Screen;
|
||||
struct Semaphore;
|
||||
struct SignalSemaphore;
|
||||
struct SimpleSprite;
|
||||
struct TagItem;
|
||||
struct Task;
|
||||
struct TextAttr;
|
||||
struct TextExtent;
|
||||
struct TextFont;
|
||||
struct timeval;
|
||||
struct UCopList;
|
||||
struct View;
|
||||
struct ViewPort;
|
||||
struct VSprite;
|
||||
struct WBObject;
|
||||
struct Window;
|
||||
|
||||
struct bltnode;
|
||||
struct cprlist;
|
||||
struct gpLayout;
|
||||
struct dtPrint;
|
||||
|
||||
#endif /* __INLINE_STUB_H */
|
||||
|
|
@ -91,6 +91,18 @@ def headers_install():
|
|||
copytree('{sources}/{ixemul}/include', '{prefix}/{target}/libnix/include')
|
||||
|
||||
|
||||
@recipe('fd2sfd-install')
|
||||
def install_fd2sfd():
|
||||
info('installing fd2sfd')
|
||||
|
||||
mkdir('{prefix}/{target}/ndk/include/inline')
|
||||
|
||||
copy('{build}/fd2sfd/fd2sfd', '{prefix}/bin')
|
||||
for header in ['m68k-amigaos/macros.h', 'm68k-amigaos/alib.h', 'stubs.h']:
|
||||
copy(path.join('{build}/fd2sfd/cross/share', header),
|
||||
'{prefix}/{target}/ndk/include/inline')
|
||||
|
||||
|
||||
@recipe('fd2pragma-install')
|
||||
def install_fd2pragma():
|
||||
info('installing fd2pragma')
|
||||
|
|
@ -361,7 +373,7 @@ def build():
|
|||
unpack('fd2sfd', work_dir='{build}')
|
||||
configure('fd2sfd', '--prefix={prefix}', from_dir='{build}/fd2sfd')
|
||||
make('fd2sfd')
|
||||
make('fd2sfd', 'install')
|
||||
install_fd2sfd()
|
||||
|
||||
unpack('fd2pragma', work_dir='{build}')
|
||||
make('fd2pragma')
|
||||
|
|
|
|||
Loading…
Reference in New Issue