Otherwise all new nodes get assigned to IRQ#0. Note: it may not be correct
to set GSI to the same value as IRQ by default. Testing on number of board
did not show any issues though.
Problem visible on Gigabyte GA-H55M-S2H where _CRS has different
polarity/trigger setting than MADT. This resulted in interrupt being
configured as LOW/LEVEL while BIOS was expecting HIGH/LEVEL (from MADT)
and interrupt was kept being raised all the time.
Check uses SMBIOS tables, reading product name from System information
table (type 0x1).
Note: SMBIOS possibly could become a separate .resource in future.
Interrupt handlers and soft interrupt code is required to preserve the
remaining XMM registers 5-15. This is a balance between saving all
registers vs saving none and requiring all code to be strictly controlled.
This allows to use limited optimizations in interrupt handling code -
for example CopyMem uses these four SSE registers for faster operations.
Also some vectorization code can use SSE, but it's needs to be strictly
controlled. To guarantee no SSE registers are being used,
add -general-regs-only when compiling code.
Doing this guarantees that kernel code does not modify values of SSE/AVX
registers when executing interrupt handler code. SSE/AVX are not part
of of register frame saved when entering interrupt handler code.
Note: generic interrupt handler code will call into specific driver
interrupt handlers (or software interrupt code executed via Cause). This
code can also be writing to SSE/AVX registers and damaging them. This
case is not handled in this commit.
This can happen if a device driver didn't provide reset handler and device
keeps on raising interrupts.
"System Shutdown" reset handler is installed now in PREINITLIB (before
first Enable()) and ShutdownA has a simplified added for emergency
situations. Code in Exec_ExtAlert already detects and issues emergency
shutdown.
# The instance doesnt guarantee the order in which the IRQs are handled by the IOAPIC's - just the order they are listed in the ACPI tables.
# Older obscure devices may not start with the first ISA IRQ, but leave the PIC handling some. Instead check if the base, and base+pin are within the ISA range and apply the adjustments if necessary.
