mirror of
https://github.com/weiju/amiga-stuff
synced 2025-11-23 19:01:45 +00:00
273 lines
8.7 KiB
Python
273 lines
8.7 KiB
Python
import struct
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ADDR_MODES = {
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'000': 'Dn', '001': 'An', '010': '(An)', '011': '(An)+', '100': '-(An)',
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'101': '(d16,An)', '110': '(d8,An,Xn)', '111': 'EXT' # -> ADDR_MODES_EXT
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}
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ADDR_MODES_EXT = {
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'000': '(xxx).W', '001': '(xxx).L', '100': '#<data>',
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'010': '(d16,PC)', '011': '(d8,PC,Xn)'
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}
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OPCODE_CATEGORIES = {
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'0000': 'bitops_movep_imm', '0001': 'move.b', '0010': 'move.l', '0011': 'move.w',
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'0100': 'misc', '0101': 'addq_subq', '1001': 'sub_subx',
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'0110': 'bcc_bsr_bra', '0111': 'moveq',
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'1101': 'add_addx'
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}
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ADD_SUB_OPMODES = {
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'000': ('b', 'ea,dn->dn'), '001': ('w', 'ea,dn->dn'),'010': ('l', 'ea,dn->dn'),
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'100': ('b', 'dn,ea->ea'), '101': ('w', 'dn,ea->ea'),'110': ('l', 'dn,ea->ea')
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}
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SIZES = ['b', 'w', 'l']
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CONDITION_CODES = [
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't', 'f', 'hi', 'ls',
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'cc', 'cs', 'ne', 'eq',
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'vc', 'vs', 'pl', 'mi',
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'ge', 'lt', 'gt', 'le'
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]
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class Opcode(object):
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def __init__(self, name, size):
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self.name = name
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self.size = size
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def is_branch(self):
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return False
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def __repr__(self):
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return "%s" % self.name
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class Operation2(Opcode):
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def __init__(self, name, size, src, dest):
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Opcode.__init__(self, name, size)
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self.src = src
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self.dest = dest
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def __repr__(self):
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return "%s\t%s,%s" % (self.name, self.src, self.dest)
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class Operation1(Opcode):
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"""A single operand operation"""
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def __init__(self, name, size, dest):
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Opcode.__init__(self, name, size)
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self.dest = dest
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def __repr__(self):
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return "%s\t%s" % (self.name, self.dest)
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class Jump(Opcode):
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def __init__(self, name, size, displacement):
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Opcode.__init__(self, name, size)
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self.displacement = displacement
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def is_branch(self):
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return True
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def __repr__(self):
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return "%s\t%s" % (self.name, self.displacement)
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def is_move(category):
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return category in {'move.b', 'move.w', 'move.l'}
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def next_word(size, data, data_offset):
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if size == 'L':
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value = struct.unpack('>i', data[data_offset:data_offset+4])[0]
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added = 4
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elif size == 'W':
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data[data_offset:data_offset+2]
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value = struct.unpack('>h', data[data_offset:data_offset+2])[0]
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added = 2
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else:
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raise Exception('unsupported size: ', size)
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return (value, added)
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def operand(size, mode_bits, reg_bits, data, offset):
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result = ""
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added = 0
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mode = ADDR_MODES[mode_bits]
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size = size.upper()
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if mode == 'EXT':
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mode = ADDR_MODES_EXT[reg_bits]
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regnum = int(reg_bits, 2)
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if mode == '#<data>':
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imm_value, added = next_word(size, data, offset + 2)
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result = "#%d" % imm_value
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elif mode in {'(xxx).L', '(xxx).W'}: # absolute
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addr, added = next_word(mode[-1], data, offset + 2)
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result = "%d.%s" % (addr, mode[-1])
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elif mode == '(d16,PC)':
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disp16, added = next_word('W', data, offset + 2)
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result = "%d(PC)" % disp16
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else:
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raise Exception("unsupported ext mode: '%s'" % mode)
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elif mode == '(d16,An)':
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regnum = int(reg_bits, 2)
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disp16, added = next_word('W', data, offset + 2)
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result = "%d(A%d)" % (disp16, regnum)
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else:
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regnum = int(reg_bits, 2)
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result = mode.replace('n', str(regnum))
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return result, added
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def disassemble_move(bits, data, offset):
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category = OPCODE_CATEGORIES[bits[0:4]]
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total_added = 2
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# dst: reg|mode
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dst_op, added = operand(category[-1], bits[7:10], bits[4:7], data, offset)
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total_added += added
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# src: mode|reg
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src_op,added = operand(category[-1], bits[10:13], bits[13:16], data, offset)
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total_added += added
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return Operation2(category, total_added, src_op, dst_op)
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def disassemble_add_sub(name, bits, data, offset):
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total_added = 2
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reg = "D%d" % int(bits[4:7], 2)
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size, operation = ADD_SUB_OPMODES[bits[7:10]]
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ea, added = operand(size, bits[10:13], bits[13:16], data, offset)
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total_added += added
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if operation == 'ea,dn->dn':
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src = ea
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dst = reg
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elif operation == 'dn,ea->ea':
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src = reg
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dst = ea
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else:
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raise Exception('Unknown operation for %s' % name)
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return Operation2('%s.%s' % (name, size), total_added, src, dst)
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def disassemble_misc(bits, data, offset):
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#print("misc bits: " + bits)
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if bits == '0100111001110101': # rts
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return Opcode('rts', 2)
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elif bits == '0100101011111100': # illegal
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return Opcode('illegal', 2)
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elif bits[7:10] == '111': # lea
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regnum = int(bits[4:7], 2)
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ea, added = operand('l', bits[10:13], bits[13:16], data, offset)
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return Operation2('lea', added + 2, ea, 'A%d' % regnum)
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elif bits.startswith('0100111010'): # jsr
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ea, added = operand('l', bits[10:13], bits[13:16], data, offset)
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return Jump('jsr', added + 2, ea)
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elif bits.startswith('0100111011'): # jmp
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ea, added = operand('l', bits[10:13], bits[13:16], data, offset)
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return Jump('jmp', added + 2, ea)
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elif bits.startswith('01001010'): # tst.x
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size = SIZES[int(bits[8:10], 2)]
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ea, added = operand('l', bits[10:13], bits[13:16], data, offset)
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return Operation1('tst.%s' % size, added + 2, ea)
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else:
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print("unrecognized misc: %s" % bits)
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raise Exception('TODO Misc')
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def signed8(value):
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return -(256 - value) if value > 127 else value
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def branch_displacement(bits, data, offset):
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"""disp, added = read displacement"""
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disp = signed8(int(bits[8:16], 2))
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if disp == 0: # 16 bit displacement
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return next_word('W', data, offset + 2)
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elif disp == -1: # 32 bit displacement
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return next_word('L', data, offset + 2)
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else:
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return disp, 0
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def _disassemble(data, offset):
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bits = "{0:016b}".format(struct.unpack(">H", data[offset:offset+2])[0])
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# first step categorize by looking at bits 15-12
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opcode = bits[0:4]
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category = OPCODE_CATEGORIES[opcode]
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if is_move(category):
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instr = disassemble_move(bits, data, offset)
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elif category in {'add_addx', 'sub_subx'}:
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if bits[7] == 1 and bits[10:12] == '11': # extended
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raise Exception('addx/subx not supported yet')
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else:
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instr = disassemble_add_sub(category[0:3], bits, data, offset)
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elif category == 'misc':
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instr = disassemble_misc(bits, data, offset)
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elif category == 'moveq':
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regnum = int(bits[4:7], 2)
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value = signed8(int(bits[8:16], 2))
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instr = Operation2('moveq', 2, "#%d" % value, 'D%d' % regnum)
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elif category == 'bcc_bsr_bra':
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if bits[0:8] == '01100000': # bra
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disp, added = branch_displacement(bits, data, offset)
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instr = Jump('bra', added + 2, disp)
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elif bits[0:8] == '01100001': # bsr
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disp, added = branch_displacement(bits, data, offset)
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instr = Jump('bsr', added + 2, disp)
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else:
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cond = CONDITION_CODES[int(bits[4:8], 2)]
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disp, added = branch_displacement(bits, data, offset)
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instr = Jump('b%s' % cond, added + 2, disp)
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elif category == 'addq_subq':
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if bits[7] == '0': # addq
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ea, added = operand('l', bits[10:13], bits[13:16], data, offset)
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value = int(bits[4:7], 2)
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instr = Operation2('addq', added + 2, '#%d' % value, ea)
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else:
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raise Exception('TODO addq_subq etc')
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else:
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print("\nUnknown instruction\nCategory: ", category, " Bits: ", bits)
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raise Exception('TODO')
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return instr
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def print_instruction(address, op):
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print("$%08x:\t%s" % (address, op))
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"""
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if len(op) == 3:
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opcode, src, dst = op
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print("$%08x:\t%8s %s,%s" % (address, opcode, src, dst))
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elif len(op) == 2:
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opcode, ea = op
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print("$%08x:\t%8s %s" % (address, opcode, ea))
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elif len(op) == 1:
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print("$%08x:\t%8s" % (address, op[0]))
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else:
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raise Exception("can't print instruction with %d components" % len(op))
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"""
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def disassemble(code):
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"""Disassembling a chunk of code works on this assumptions:
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1. the first address in the block contains a valid instruction from here
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a. branches: add the displacement target to the list of continue points
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b. if the instruction is an absolute jump/branch, we can't safely
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assume the code after the instruction is valid -> continue at branch
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target
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c. conditional branch -> add the address after the instruction as a valid
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ass valid decoding location
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d. rts: we can't assume the code after this instruction is valid
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"""
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offset = 0
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while offset < len(code):
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instr = _disassemble(code, offset)
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print_instruction(offset, instr)
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offset += instr.size
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