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208 lines
6.5 KiB
C
208 lines
6.5 KiB
C
/*
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Copyright (C) 2010-2011, The AROS Development Team. All rights reserved.
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Desc: GetCPUInfo() - Provides information about installed CPUs
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*/
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#define DEBUG 0
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#include <aros/debug.h>
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#include <exec/types.h>
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#include <aros/libcall.h>
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#include <proto/utility.h>
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#include <resources/processor.h>
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#include "defaults.h"
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#include "processor_intern.h"
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/*****************************************************************************
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NAME */
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#include <proto/processor.h>
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AROS_LH1(void, GetCPUInfo,
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/* SYNOPSIS */
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AROS_LHA(struct TagItem *, tagList, A0),
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/* LOCATION */
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struct ProcessorBase *, ProcessorBase, 1, Processor)
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/* FUNCTION
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Provides information about selected processor in the system
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INPUTS
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Function takes an array of tags. Data is returned for each tag. See
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specific tag description. There is a control tag CGIT_SelectedProcessor.
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TAGS
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GCIT_SelectedProcessor - (ULONG) When this tag is set correctly, information
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about choosen processor is provided. If this
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tag is missing or this tag has invalid value,
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information about first processor is returned.
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GCIT_NumberOfProcessors - (ULONG *) Provides the number of processors
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present in the system.
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GCIT_ModelString - (CONST_STRPTR *) Provides the name of the model of the
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processor. The string is considered read-only.
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GCIT_Family - (ULONG *) Provides designation of processor family using
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one of the CPUFAMILY_XXX values.
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GCIT_VectorUnit - (ULONG *) Provides designation of available vectory
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unit using one of the VECTORTYPE_XXX values.
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GCIT_Architecture - (ULONG *) Provides designation of processor
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architecture using one of the PROCESSORARCH_XXX
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values.
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GCIT_Endianness - (ULONG *) Provides designation of current processor
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endianness using one of the ENDIANNESS_XXX values.
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GCIT_ProcessorSpeed - (UQUAD *) Provides the current CPU speed in Hz
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GCIT_FrontsideSpeed - (UQUAD *) Provides the current FSB speed in Hz
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GCIT_ProcessorLoad - (ULONG *) Provides the current CPU load (0-0xffffffff)
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Cache sizes - (ULONG *) Following tags are used to retrieve size of
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specified caches.
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GCIT_L1CacheSize
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GCIT_L1DataCacheSize
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GCIT_L1InstructionCacheSize
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GCIT_L2CacheSize
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GCIT_L3CacheSize
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Size is returned in kB.
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GCIT_CacheLineSize - (ULONG *) Provides the size of cache line in bytes.
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In case these sizes differ per cache level, the
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smallest size if provided.
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Features - (BOOL *) Following tags are used to check availability of
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certain features. The result is always a boolean.
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GCIT_SupportsFPU
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GCIT_SupportsAltiVec
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GCIT_SupportsVMX
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GCIT_SupportsMMX
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GCIT_SupportsMMXEXT
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GCIT_Supports3DNOW
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GCIT_Supports3DNOWEXT
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GCIT_SupportsSSE
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GCIT_SupportsSSE2
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GCIT_SupportsSSE3
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GCIT_SupportsSSSE3
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GCIT_SupportsSSE41
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GCIT_SupportsSSE42
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GCIT_SupportsSSE4A
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GCIT_SupportsVME
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GCIT_SupportsPSE
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GCIT_SupportsPAE
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GCIT_SupportsCX8
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GCIT_SupportsAPIC
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GCIT_SupportsCMOV
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GCIT_SupportsPSE36
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GCIT_SupportsCLFSH
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GCIT_SupportsACPI
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GCIT_SupportsFXSR
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GCIT_SupportsHTT
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GCIT_SupportsCX16
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GCIT_SupportsVirtualization
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GCIT_SupportsNoExecutionBit
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GCIT_Supports64BitMode
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GCIT_SupportsMSR
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RESULT
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None
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NOTES
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EXAMPLE
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BUGS
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SEE ALSO
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INTERNALS
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******************************************************************************/
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{
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AROS_LIBFUNC_INIT
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struct TagItem * passedTag = NULL;
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/* This is the default implementation */
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while ((passedTag = NextTagItem(&tagList)) != NULL)
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{
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if ((passedTag->ti_Tag > GCIT_FeaturesBase) &&
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(passedTag->ti_Tag <= GCIT_FeaturesLast))
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{
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*((BOOL *)passedTag->ti_Data) = FALSE;
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continue;
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}
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else
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{
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switch(passedTag->ti_Tag)
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{
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case(GCIT_NumberOfProcessors):
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*((ULONG *)passedTag->ti_Data) = ProcessorBase->cpucount;
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break;
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case(GCIT_ModelString):
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*((CONST_STRPTR *)passedTag->ti_Data) = "Unknown";
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break;
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case(GCIT_Family):
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*((ULONG *)passedTag->ti_Data) = CPUFAMILY_UNKNOWN;
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break;
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case(GCIT_VectorUnit):
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*((ULONG *)passedTag->ti_Data) = VECTORTYPE_NONE;
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break;
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case(GCIT_L1CacheSize):
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*((ULONG *)passedTag->ti_Data) = 0;
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break;
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case(GCIT_L1DataCacheSize):
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*((ULONG *)passedTag->ti_Data) = 0;
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break;
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case(GCIT_L1InstructionCacheSize):
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*((ULONG *)passedTag->ti_Data) = 0;
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break;
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case(GCIT_L2CacheSize):
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*((ULONG *)passedTag->ti_Data) = 0;
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break;
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case(GCIT_L3CacheSize):
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*((ULONG *)passedTag->ti_Data) = 0;
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break;
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case(GCIT_CacheLineSize):
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*((ULONG *)passedTag->ti_Data) = 0;
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break;
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case(GCIT_Architecture):
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*((ULONG *)passedTag->ti_Data) = PROCESSORARCH_DEF;
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break;
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case(GCIT_Endianness):
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*((ULONG *)passedTag->ti_Data) = ENDIANNESS_DEF;
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break;
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case(GCIT_ProcessorSpeed):
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*((UQUAD *)passedTag->ti_Data) = 0;
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break;
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case(GCIT_ProcessorLoad):
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*((ULONG *)passedTag->ti_Data) = 0;
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break;
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case(GCIT_FrontsideSpeed):
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*((UQUAD *)passedTag->ti_Data) = 0;
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break;
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}
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}
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}
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AROS_LIBFUNC_EXIT
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} /* GetCPUInfo() */
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